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Chip Design Authors: Jason Bloomberg, Trevor Bradley, David Strom

Related Topics: Datacenter Automation, Chip Design

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Azuro’s Low Power CTS Tool Included in TSMC’s Integrated Sign-Off Flow

Azuro, Inc., the provider of advanced optimization tools for nanometer chip design, today announced the inclusion of its PowerCentric™ low power clock tree synthesis tool in TSMC’s new Integrated Sign-Off Flow. The Integrated Sign-Off Flow is an automated RTL to GDSII chip implementation flow that tightly integrates TSMC foundry technology files, pre-qualified library, IP, EDA tools, and sign-off margin recommendations into a fully automated scripted production-quality flow that has been proven and refined over hundreds of applications.

“Rising design setup costs and design cycle times are critical challenges for the semiconductor industry,” said ST Juang, senior director of Design Infrastructure Marketing at TSMC. “The TSMC Integrated Sign-Off Flow brings together parties across the entire chip design ecosystem into a tightly controlled fully automated platform for achieving best in class silicon quickly and with lowest cost.”

Azuro and TSMC worked closely during the development and beta testing of the Integrated Sign-Off Flow to ensure that the insertion of PowerCentric into the Flow was completely transparent to Flow users. Using the Integrated Sign-Off Flow, chip design teams taping out to TSMC’s foundries can adopt Azuro’s unique low power CTS capability within an extensively pre-tested pre-integrated production-ready flow including a full set of automated scripts and user documentation.

“Integration is vital to continued growth and profitability of the chip design industry,” said Paul Cunningham, co-founder and CEO of Azuro. “The Integrated Sign-Off Flow enables a tightly integrated flow to be delivered which can contain components from multiple ecosystem parties. Through the TSMC Integrated Sign-Off Flow, PowerCentric can be adopted more broadly and with less effort than as a stand-alone solution.”

About Azuro

Azuro is an electronic design automation (EDA) company supplying software tools to design digital semiconductor chips. The company's unique clock tree synthesis and physical optimization technologies make chips faster, reduce chip power and dramatically accelerate chip time to market. Customers of Azuro's software include Broadcom, Cambridge Silicon Radio, NVIDIA, ST Microelectronics, and Texas Instruments. The company was founded in 2002, and has completed over 40 tapeouts since launching its first product in 2005. Azuro is headquartered in Santa Clara, CA with R&D in Cambridge, UK, and is privately held. For additional information, please visit www.azuro.com.

Azuro, PowerCentric, Rubix and the Azuro logo are either trademarks or registered trademarks of Azuro, Inc. All other trademarks are the property of their respective owners.

Keywords: clock tree synthesis, TSMC, integrated sign-off flow, semiconductor fabrication, semiconductor foundry, low power, semiconductor, integrated circuit, IC, electronic design automation, EDA, PowerCentric, Azuro

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