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K-micro Announces Availability of FPGA Board for the CatsEye Development Systems

Addition of FPGA boards significantly reduces design time for complex ASICs

SAN JOSE, Calif., March 16 /PRNewswire/ -- K-micro (Kawasaki Microelectronics America, Inc.), a leader in advanced ASICs, announced the availability of FPGA boards for the CatsEye development systems to speed up the hardware and software development time associated with complex ASIC designs.

The FPGA board is used by CatsEye developers to readily add their logic to the platform CatsEye chip. This enables the developer to fully integrate and test their IP in the CatsEye platform before releasing the design to fabrication. The FPGA Development boards include a Xilinx Virtex-4 XC4VLX200(TM) and a K-micro PCI Express PIPE PHY chip, plus a variety of interfaces. Using standard tools, the designers can readily add their "secret sauce", and verify the operation before releasing the chip design.

"Our customers will be able to fully model their ASIC in a fraction of the time normally required to integrate their IP into a new chip," said Joel Silverman, vice president of technology solutions at K-micro. "The XC4VLX200 has 200K Logic cells, the equivalent of about 1.4 million ASIC gates, and can be used to model complex logic that will be integrated into the ASIC. Integration and verification time is greatly reduced and combined with concurrent software development results in typical saving of 12 months on a complex ASIC design. Advanced design and development tools enable our customers to rapidly add, remove or replace any of the IP with their own or a third party IP. The flexibility of the OCP interface facilitates IP reusability and helps to reduce design time."

The FPGA board connects to the CatsEye Development system board via a high speed OCP inter-board connection. By using standard tools, developers can easily add their logic to the FPGA and simulate their complete chip. If more gates are needed, an additional FPGA board can be stacked on top of the first board.

The CatsEye chip is an advanced SoC that contains a complete CPU subsystem with two MIPS32(R) 24Kf(TM) cores, two 10/100/1000 Mbit Ethernet MACs, security processor, memory controllers and host of other peripherals that are required for SoC developments. "When this powerful processing engine is combined with the flexibility of the FPGA board and the easy-to-use development tools, the engineer is free to concentrate on the design and not have to worry about the development environment," added Silverman.

About K-micro (Kawasaki Microelectronics America, Inc.)

K-micro's innovative ASIC technologies and world-class design support are used in the consumer electronics, computer, office-automation, networking and storage markets. The company is an active participant in industry standards organizations, including InterNational Committee for Information Technology Standards (INCITS) Technical Committee T10 for SCSI Storage Interfaces, Optical Internetworking Forum (OIF), PCI Special Interest Group (PCI-SIG), USB Implementers Forum, Digital Living Network Alliance (DLNA), Universal Plug and Play Forum (UPnP), the Digital Display Working Group (DDWG), Home Phoneline Networking Alliance (HomePNA), Multimedia over Coax Alliance (MoCA), and OCP International Partnership (OCP-IP). K-micro has design centers in San Jose, Taipei, and Tokyo. For more information, contact the company at 408-570-0555, or visit http://www.k-micro.us

MIPS, MIPS32, 24Kc, 24Kf, 24KEc, 24KEf, 34Kc, 34Kf, 74Kc, 74Kf and MIPS-Based are trademarks or registered trademarks in the United States and other countries of MIPS Technologies, Inc. XILINX, the Xilinx logo, Virtex 4, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks referred to herein are the property of their respective owners.

SOURCE K-micro

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