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Chip Design Authors: Jason Bloomberg, Trevor Bradley, David Strom

Related Topics: Chip Design

Chip Design: News Feed Item

Silistix Leads Participation in Power Domain Management Panel, Presents Network-on-Chip Innovations at MultiCore Expo 2009 in Santa Clara

SAN JOSE, CA -- (Marketwire) -- 03/11/09 --

What:   Silistix Inc. Senior Architect, Robert Adair, will take part in a
        panel entitled "Clock & Power Domain Control/Management Challenges
        in a MultiCore World: The Interconnect Dilemma" at the MultiCore
        Expo Conference in the Santa Clara Convention Center. Silistix
        proposed the topic and authored the abstract for the panel that
        will be moderated by industry veteran Ron Wilson, Executive
        Director, EDN Magazine. Joining Mr. Adair on the panel will be
        industry experts from MIPS, Synopsys, and Sonics.

        Additionally, Silistix Director of Product Marketing, David
        Stratman, will present a talk titled "Managing SoC Complexity Using
        'True' Globally Asynchronous, Locally Synchronous Interconnect
        Technologies" outlining Network-on-Chip (NoC) innovations recently
        made available in CHAIN®works 3.0.

        Silistix staff will be available throughout the conference at booth
        #30 to answer questions about both the panel and presentation or
        demo their award winning CHAIN®works family of Network-on-Chip
        silicon IP and tools. Abstracts available on both Silistix and
        MultiCore websites.

When:   March 18th 2009 (Wednesday)
        Presentation: 2:20 PM PT
        Panel:  4:20 PM PT

Where:  MultiCore Expo 2009
        Santa Clara Convention Center
        5001 Great America Parkway, Santa Clara, CA
        Silistix Booth #30
        www.multicore-expo.com

About Silistix

Silistix, Inc. is a leading Silicon Intellectual Property (SIP) vendor, delivering predictable Network-on-Chip (NoC) solutions for managing chip complexity. Silistix CHAIN®works family of tools and IP libraries address timing closure, power management, and deep-sub-micron process variability while cutting chip design time and effort. Silistix is privately held and is backed by a number of venture firms and corporate investors, including Intel Capital. The company has offices in Manchester, England; San Jose, California; and Tokyo, Japan. For more information, visit www.silistix.com.

Silistix and CHAIN are registered trademarks of Silistix, Inc. All other trademarks are property of their respective owners.

For more information:
David Stratman
Dir. Product Marketing
+1 408 453-8400
Email Contact

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