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Chip Design Authors: Jason Bloomberg, Trevor Bradley, David Strom

Related Topics: CEOs in Technology, Consumer Electronics, Chip Design, CES 2010 on Ulitzer

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Atrenta Announces a New Text Book on Timing Constraints

Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced the availability of a comprehensive text book on timing constraints. The book “Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)” is authored by Sridhar Gangadharan, senior product director at Atrenta and Sanjay Churiwala, director at Xilinx. The book, which features a foreword by Dr. Ajoy Bose, chairman, president and CEO of Atrenta, is being published by Springer Science+Business Media.

“Timing has become a critical requirement for the highly complex system on chip designs we see today and effective use of SDC is critical to success,” said Sridhar Gangadharan. “I would like to acknowledge Synopsys for their work to develop the Synopsys Design Constraints (SDC) format and their willingness to make it widely available through their TAP-in program.”

The book targets system on chip designers and provides a complete overview of how to create effective timing constraints using SDC, including detailed syntax and semantics, its impact on timing analysis and synthesis and the interaction of timing constraints with the rest of the design flow.

“Our goal was to develop a practical, hands-on guide to writing and understanding timing constraints for system on chip design,” said Sanjay Churiwala. “While there are texts that treat portions of the problem such as synthesis or static timing analysis, there has not been a single, highly detailed source that treats the entire set of timing constraints challenges specifically relating to SDC.”

The book is available now through Springer (www.springer.com) or at www.amazon.com.

About Atrenta

Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.

SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com

© 2013 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo and SpyGlass are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

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