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Chip Design Authors: Jason Bloomberg, Trevor Bradley, David Strom

Related Topics: Datacenter Automation, Chip Design

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SpringSoft’s Third Generation Laker Custom IC Design Platform Included in TSMC 20nm Custom Design Reference Flow

SpringSoft, Inc., a global supplier of specialized IC design software, today announced that the Laker3™ Custom IC Design Platform has been included in TSMC's 20-nanometer (nm) Custom Design Reference Flow.

The TSMC 20nm Custom Design Reference Flow features best-in-class design tools and methodologies that address the challenges of 20nm chip design and verification. SpringSoft enables design success with its third generation Laker product family that provides a complete OpenAccess (OA) design and layout environment optimized for performance and interoperability in 20nm custom digital, analog and mixed-signal flows.

Laker 20nm advancements include new double patterning-aware design and voltage-dependent design rule checking (DRC) flows, enhanced flows for layout-dependent effect (LDE) and parasitic-aware layout, and advanced gradient density analysis capabilities. SpringSoft also collaborated with Mentor Graphics Corporation to qualify Laker-Calibre RealTime integration for signoff-quality, real-time DRC during custom layout.

“Laker is in 20nm production and development projects at leading-edge companies around the world. Now, our latest generation Laker custom design and layout technologies are supported with 20nm flows optimized for TSMC’s latest process technology and design ecosystem,” said Dave Reed, senior director of marketing for custom IC design solutions at SpringSoft.

”Combining advanced automation and high accuracy, SpringSoft makes a valuable contribution to TSMC’s 20nm Custom Design Reference Flow,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division.

20nm Custom Design and Layout Flows

SpringSoft’s Laker Advanced Design Platform (ADP) and Custom Layout software works with other EDA tools in highly automated workflows. These provide designers with continuous, practical feedback throughout the design process. Laker custom layout capability is applied to key flows and advanced tools in:

  • Double patterning-aware design flow with real-time DRC to find/fix double patterning violations, pre-coloring to simulate/manipulate mask decomposition to manage parasitic of critical paths during layout editing;
  • LDE-aware design flow with on-the-fly constraint checking to monitor the LDE impact on performance;
  • Parasitic-aware layout flow with interactive parasitic display and automated RC constraint checking to close the gap between pre-and post-layout simulation results;
  • Voltage-dependent DRC (VDRC) flow with automatic voltage configuration from simulation results for layout operations; and
  • Gradient density analysis with layer-specific calculations and mapping to check and fix issues.

About SpringSoft

SpringSoft, Inc. (TAIEX: 2473) is a global supplier of innovative automation technologies for the design and verification of complex digital, analog and mixed-signal SoCs. Its award-winning product portfolio is used by more than 400 of today's leading semiconductor companies, foundries, and electronic systems OEMs. Headquartered in Hsinchu, Taiwan, SpringSoft is the largest company in Asia specializing in IC design software and a recognized industry leader in customer service with multiple R&D sites and local support offices around the world. For more information, visit www.springsoft.com.

Laker3 and Laker are trademarks of SpringSoft, Inc. All other trademarks or registered trademarks are the property of their respective owners.

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