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Chip Design Authors: Jnan Dash, Jason Bloomberg, Trevor Bradley, David Strom

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TSMC Includes Azuro Vectorless Power Analysis and Multi-Corner CTS in Reference Flow 10.0

Azuro, Inc., a provider of software tools for semiconductor chip design, today announced that Taiwan Semiconductor Manufacturing Company (TSMC) has included Azuro’s PowerCentric™ multi-corner CTS and SASim™ vectorless power analysis as part of TSMC’s Reference Flow 10.0.

“Azuro’s vectorless power analysis provides chip designers a comprehensive power analysis capability which is essential for optimizing low-power designs,” said ST Juang, senior director of Design Infrastructure Marketing, TSMC. “PowerCentric multi-corner CTS helps manage designer productivity in the face of a growing number of timing corners.”

Average power - a measure of chip battery life - is dependent on circuit activity, which is difficult to obtain early in the design cycle. PowerCentric’s SASim can be run in 100% vectorless mode, or 100% vectored mode, or in a hybrid mode that uses RTL vectors. SASim supports a complete methodology for analyzing average dynamic power and leakage power. Circuit activity can be analyzed with sophisticated GUI-driven visualizations.

At 65nm and below, gate delays and wire delays no longer scale in the same way with changing operating conditions. This means that a clock balanced in one timing corner will not be balanced in another timing corner. Therefore, it has become imperative for CTS to build clock trees that are balanced in multiple corners simultaneously.

“Adding Azuro’s multi-corner CTS and vectorless power analysis to Reference Flow 10.0 establishes our technology as the accepted standard for mainstream design,” said Paul Cunningham, co-founder and CEO of Azuro. “We look forward to continuing our partnership with TSMC to support the design needs of our customers.”

About Azuro

Azuro is an electronic design automation (EDA) company supplying software tools to design digital semiconductor chips. The company’s unique clock tree synthesis and physical optimization technologies make chips faster, reduce chip power and dramatically accelerate chip time to market. Customers of Azuro’s software include Broadcom, Cambridge Silicon Radio, NVIDIA, NXP, STMicroelectronics, and Texas Instruments. Founded in 2002, the company is headquartered in Santa Clara, CA with R&D in Cambridge, UK, and is privately held. www.azuro.com

Azuro, PowerCentric, SASim and the Azuro logo are either trademarks or registered trademarks of Azuro, Inc. All other trademarks are the property of their respective owners.

Keywords: clock tree synthesis, TSMC, semiconductor foundry, low power, chip, integrated circuit, IC, electronic design automation, EDA, PowerCentric, Azuro, vectorless, power analysis, Reference Flow, average power, simulation vectors, battery life, chip cooling, toggle rate, dynamic power, leakage power, SASim, multi-corner, multicorner

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