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Chip Design Authors: Jnan Dash, Jason Bloomberg, Trevor Bradley, David Strom

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Satin IP Technologies, Toppan Photomasks and XYALIS Partner to Improve Design for Mask Manufacturing

Satin IP Technologies SAS, Toppan Photomasks France SAS and XYALIS SaRL have collaborated within the Crystal partnership program to significantly improve design for mask manufacturing (DFMM) by breaking the barriers that have traditionally separated integrated chip (IC) designers from mask shop engineers. Crystal is a European collaborative R&D program sponsored by the Cluster for Application and Technology Research in Europe on NanoElectronics (CATRENE). Other participants include Atmel and CEA-LETI.

While the old design rule checkers (DRC) developed into sophisticated and pro-active design for manufacturing (DFM) tool suites, the mask rules checks are still implemented at the final phase when the GDSII data is released. Resolution enhancement techniques (RET) and optical proximity correction (OPC) further restrict the ability to revise the design or even to take into account the mask manufacturability issues for an additional design cycle.

One of the Crystal work packages is devoted to identification and formalization of recommended design practices to make mask manufacturing a more efficient and less iterative process. Crystal will also provide the tools to deploy and monitor those practices throughout the design chain.

“Designing chips so that photomasks can be manufactured more easily is a complex challenge that cannot be solved without tight collaboration between chip design teams, semiconductor fabs, mask shops and EDA vendors,” said Michel Tissier, European technology integration director at Toppan Photomasks France and head of the Crystal program. “By making these different groups work with Satin IP’s VIP Lane on real manufacturing data, Crystal is expected to help improve design consistency, on-time delivery and the cost of photomask design.”

Michel Tabusse, founder and CEO of Satin IP Technologies, said, “It is Satin IP’s core business to help deploy and improve design quality practices throughout semiconductor companies with maximum adoption rate by the design teams. Crystal will give us access to real data about the manufacturing challenges at mask shops and about the design practices in the upstream design phases that would solve these challenges. We plan to use these data to create an unmatched library of DFMM quality checks as an add-on to VIP Lane, our design quality closure solution.”

Eric Beisser, founder and CEO of XYALIS, added, “Problems that increase the length or number of design cycles, or mistakes that cause additional re-spins of a die, can make the difference between profit and loss for a new product or even result in project cancellation. With photomask manufacturing costs representing almost 10% of global costs at the 65nm node, we expect that the DFMM practices that Crystal is documenting for the design community will be of very significant impact.”

The Crystal program was started in January 2008. A design environment prototype, offering a first set of design rules with monitoring capabilities and links to mask data preparation tools, was demonstrated during the Euro Nanoelectronics Forum in Paris (December 2-3, 2008). An updated prototype will be shown at the Satin IP booth, # 1825, at the Design Automation Conference (San Francisco, July 27-30) -- www.dac.com/46th/index.aspx

About Satin IP Technologies

Committed to design quality closure with fast return on investment (ROI), Satin IP Technologies delivers software solutions for fact-based design quality monitoring. Working within customers' design flows, VIP Lane® turns customers' existing design practices for IP blocks or SoCs into a robust set of quality criteria and automates the implementation and documentation of design quality metrics at no extra cost in engineering time or resources. VIP Lane® shortens time-to-market by delivering effective flow integration and on-the-fly quality monitoring at zero overhead to design teams. Satin IP is a privately-held company with headquarters in Montpellier, France. For more information, see www.satin-ip.com

About Toppan Photomasks

Toppan Photomasks, Inc. is a wholly owned subsidiary of Toppan Printing Co., Ltd. a diversified global company with revenue in excess of $13 billion in fiscal 2007. Toppan Photomasks is part of the Toppan Group of photomask companies. As the world’s premier photomask provider, the Toppan Group operates the industry’s most advanced and largest network of manufacturing facilities and offers a comprehensive range of photomask technologies and research and development capabilities to meet the increasingly sophisticated and divergent product and service requirements of the global semiconductor industry. Toppan Photomasks is headquartered in Round Rock, Texas. For more information visit www.photomask.com


Established in 1998, XYALIS is privately held company, headquartered in Grenoble, France. XYALIS expertise and its success history are quite unique in the EDA industry. From the beginning, the company has focused on Design For Manufacturing tools and solutions to solve complex problems found between design and manufacturing. This area is now called DFM and is popular in the papers and symposiums. Thanks to its founders who have a very deep knowledge and experience in this field XYALIS has been able to innovate and provide new solutions to solve problems faced by engineers today. XYALIS focuses on two main flows of the layout finishing process: Metal filling to address Chemical Mechanical Polishing (CMP) issues and Mask data preparation.

XYALIS' solutions have been developed in cooperation with major semiconductor industry leaders and have been used in production for the most advanced processes (65nm and below).

For more information visit www.xyalis.com.

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